Non-volatile memory (NVM) devices have achieved widespread adoptions for code and data storage applications. An advantage of NVM devices is that they are able to retain stored data even when the power supply is interrupted. NVM devices include flash devices which can be programmed using electrical signals. A NVM cell, for example, includes a control gate (CG) and a floating gate (FG) coupled in series. The FG stores data programmed into the memory cell, while the CG selects the memory cell to be programmed or erased. Charges are stored or discharged from the FG, representing first and second states of the memory cell.
An important aspect for performance is to have high gate coupling ratio between the FG and CG to improve performance as well as reduce power consumption and cell size. However, conventional NVM devices can only achieve a gate coupling ratio of about 0.7-0.8. Such low coupling ratio limits the scalability of conventional NVM devices. In addition, low coupling ratio results in increased power consumption as well as reduced performance. For example, low gate coupling ratio results in a longer program or erase time for NVM devices.
The present disclosure is directed to a NVM cell with high gate coupling ratio to improve scalability, performance and lower power consumption.